Category Archives: papers

Papers published in peer-reviewed conferences, journals or workshops.

Processor-level Selective Replication

Posted on November 23, 2009 | Comments Off on Processor-level Selective Replication

Nithin Nakka, Karthik Pattabiraman, Zbigniew Kalbarczyk and Ravishankar Iyer, Workshop on Silicon Errors in Logic- System Effects (SELSE), 2006.
[ PDF File | Talk ]

This paper is superceded by the following conference paper.

Abstract: Even though replication has been widely used in providing fault tolerance, the underlying hardware is unaware of the application executing on it. The application cannot choose to use redundancy for a specific code section and run in a normal, unreplicated mode for the rest of the code. In this paper we propose Processor-level Selective Replication, a mechanism to dynamically configure the degree of instruction-level replication according to the applications demands. The application can choose to replicate only code sections that are critical to its crash-free execution. This decreases the impact on the performance. It is also known that many of the processor-level faults do not lead to failures observable in the application outcome. So, selective replication also decreases the number of false positives.

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FPGA Hardware Implementation of Statically Derived Error Detectors

Posted on November 23, 2009 | Comments Off on FPGA Hardware Implementation of Statically Derived Error Detectors

Peter Klemperer, Shelley Chen, Karthik Pattabiraman, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Workshop on Dependable and Secure Nanocomputing (WDSN), 2007.
[ PDF File | Talk ]

This paper is superceded by the following conference paper.

Abstract: Previous software-only error detection techniques have provided high-coverage, low-latency detection but suffer significant performance overheads with a large percentage of benign detections. This paper presents a FPGA hardware implementation of application-aware data error detectors. The detectors are automatically derived at compile time and executed in hardware at runtime, minimizing the performance overhead. We implement the static detectors using the Reliability and Security Engine, which provides a standard interface for developing reliability and security hardware modules. An initial, proof-of-concept model shows that there is only a 2% performance penalty when the detectors are implemented in hardware.

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Critical Variable Recomputation for Transient Error Detection

Posted on November 23, 2009 | Comments Off on Critical Variable Recomputation for Transient Error Detection

Karthik Pattabiraman, Zbigniew Kalbarcyk and Ravishankar Iyer, Workshop on Silicon Errors in Logic – System Effects (SELSE), 2007.
[ PDF File | Talk ]

This paper is super-ceded by the following conference paper

Abstract: This paper presents a technique to derive and implement error detectors to protect an application from data errors. The error detectors are derived automatically using compiler-based static analysis from the backward program slice of critical variables in the program. Critical variables are defined as those that are highly sensitive to errors, and deriving error detectors for these variables provides high coverage for errors in any data value used in the program. The error detectors take the form of checking expressions and are optimized for each control flow path followed at runtime. The derived detectors are implemented using a combination of hardware and software.

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Hardware Implementation of Information Flow Signatures Derived via Program Analysis

Posted on November 23, 2009 | Comments Off on Hardware Implementation of Information Flow Signatures Derived via Program Analysis

Paul Dabrowski, William Healey, Karthik Pattabiraman, Shelley Chen, Zbigniew Kalbarczyk, and
Ravishankar K. Iyer, Workshop on Dependable and Secure Nanocomputing (WDSN), 2008.
[ PDF File | Talk Slides ]

Abstract: We present an architectural solution that provides trustworthy execution of C code that computes critical data, in spite of potential hardware and software vulnerabilities. The technique uses both static compiler-based analysis to generate a signature for an application, or operating system, and dynamic hardware/software signature checking. A prototype implementation of the hardware on a soft processor within an FPGA incurs no performance overhead and about 4% chip area overhead, while the software portion of the technique adds between 1% and 69% performance overhead in our test applications, depending on the selection of critical data.

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CCC workshop invited talk

Posted on November 21, 2009 | Comments Off on CCC workshop invited talk

I was invited to speak at a workshop on Cross-Layer Resilience organized by the Computing Community Consortium (CCC).
My talk was on protecting critical infrastructure systems such as the power-grid from errors. You can find the slides here .

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Modeling Coordinated Checkpointing for Large-Scale Supercomputers

Posted on November 18, 2009 | Leave a comment

Long Wang, Karthik Pattabiraman, Lawrence Votta, Christopher Vick, Alan Wood, Zbigniew Kalbarczyk and Ravishankar Iyer, Proceedings of the International Conference on Dependable Systems and Networks (DSN), 2005.
[ PDF File | Talk ]

Abstract: Current supercomputing systems consisting of thousands of nodes cannot meet the demands of emerging high-performance scientific applications. As a result, a new generation of supercomputing systems consisting of hundreds of thousands of nodes is being proposed. However, these systems are likely to experience far more frequent failures than today’s systems, and such failures must be tackled effectively. Coordinated checkpointing is a common technique to deal with failures in supercomputers. This paper presents a model of a coordinated checkpointing protocol for large-scale supercomputers, and studies its scalability by considering both the coordination overhead and the effect of failures. Unlike most of the existing checkpointing models, the proposed model takes into account failures during checkpointing and recovery, as well as correlated failures. Stochastic Activity Networks (SANs) are used to model the system, and the model is simulated to study the scalability, reliability, and performance of the system.

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Formal Reasoning of Various Categories of Widely Exploited Security Vulnerabilities using Pointer Taintedness Semantics

Posted on November 15, 2009 | Comments Off on Formal Reasoning of Various Categories of Widely Exploited Security Vulnerabilities using Pointer Taintedness Semantics

Shuo Chen, Karthik Pattabiraman, Zbigniew Kalbarczyk and Ravishankar Iyer, Proceedings of the IFIP International Conference on Information Security (SEC), 2004.
[ PDF File | Talk ]

Abstract: This paper is motivated by a low level analysis of various categories of severe security vulnerabilities, which indicates that a common characteristic of many classes of vulnerabilities is pointer taintedness. A pointer is said to be tainted if a user input can directly or indirectly be used as a pointer value. In order to reason about pointer taintedness, a memory model is needed. The main contribution of this paper is the formal definition of a memory model using equational logic, which is used to reason about pointer taintedness. The reasoning is applied to several library functions to extract security preconditions, which must be satisfied to eliminate the possibility of pointer taintedness. The results show that pointer taintedness analysis can expose different classes of security vulnerabilities, such as format string, heap corruption and buffer overflow vulnerabilities, leading us to believe that pointer taintedness provides a unifying perspective for reasoning about security vulnerabilities.

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Toward Application-aware Security and Reliability

Posted on November 13, 2009 | Comments Off on Toward Application-aware Security and Reliability

Ravishankar Iyer, Zbigniew Kalbarczyk, Karthik Pattabiraman, William Healey, Wen-Mei Hwu, Peter Klemperer and Reza Farivar, IEEE Security and Privacy Magazine, January 2007 (Invited). [ PDF File ]

No abstract is available.

Here is a news article in the Chicago Tribune that describes this work.

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Samurai: Protecting Critical Data in Unsafe Languages

Posted on November 13, 2009 | Comments Off on Samurai: Protecting Critical Data in Unsafe Languages

Karthik Pattabiraman, Vinod Grover and Benjamin G. Zorn, Proceedings of the European Conference on Computer Systems (EuroSys), 2008.
[ PDF File | Talk ]
Continue reading →

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SymPLFIED: Symbolic Program-Level Fault Injection and Error Detection Framework

Posted on November 12, 2009 | Comments Off on SymPLFIED: Symbolic Program-Level Fault Injection and Error Detection Framework

Karthik Pattabiraman, Nithin Nakka, Zbigniew Kalbarczyk and Ravishankar Iyer, Proceedings of the International Conference on Dependable Systems and Networks (DSN), 2008.
This paper won the William C. Carter award for the best paper at the conference
[ PDF File | Talk ]
You can find the tech report for the conference paper here.


Abstract: This paper introduces SymPLFIED, a program-level framework which allows specification of arbitrary error detectors and the verification of their efficacy against hardware errors. SymPLFIED comprehensively enumerates all transient hardware errors in registers, memory and computation (expressed as value errors) that potentially evade detection and cause program failure. The framework uses symbolic execution to abstract the state of erroneous values in the program and model checking to comprehensively find all errors that evade detection. We demonstrate the use of SymPLFIED on a widely deployed aircraft collision avoidance application, tcas. Our results show that the SymPLFIED framework can be used to uncover hard-to-detect corner cases caused by transient errors in programs that may not be exposed by random fault-injection based validation.

The Coordinated Science Lab at UIUC did an article about this paper

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